Embodiments of the present invention generally relate to methods and apparatus for selective formation of epitaxial layers containing silicon, carbon and a doping material. Specific embodiments pertain to methods and apparatus for the selective formation of n-doped epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
The amount of current that flows through the channel of a MOS transistor is directly proportional to a mobility of carriers in the channel, and the use of high mobility MOS transistors enables more current to flow and consequently faster circuit performance. Mobility of the carriers in the channel of an MOS transistor can be increased by producing a mechanical stress in the channel. A channel under compressive strain, for example, a silicon-germanium channel layer grown on silicon, has significantly enhanced hole mobility to provide a pMOS transistor. A channel under tensile strain, for example, a thin silicon channel layer grown on relaxed silicon-germanium, achieves significantly enhanced electron mobility to provide an nMOS transistor.
An nMOS transistor channel under tensile strain can also be provided by forming one or more carbon-doped silicon epitaxial layers, which may be complementary to the compressively strained SiGe channel in a pMOS transistor. Thus, carbon-doped silicon and silicon-germanium epitaxial layers can be deposited on the source/drain of nMOS and pMOS transistors, respectively. The source and drain areas can be either flat or recessed by selective Si dry etching. When properly fabricated, nMOS sources and drains covered with carbon-doped silicon epitaxy imposes tensile stress in the channel and increases nMOS drive current.
It is desirable for the carbon-doped silicon epitaxial layer to contain substitutional C atoms to induce tensile strain in the channel. Higher channel tensile strain can be achieved with increased substitutional C content in a carbon-doped silicon source and drain.
Generally, sub-100 nm CMOS (complementary metal-oxide semiconductor) devices require a junction depth to be less than 30 nm. Selective epitaxial deposition is often utilized to form epitaxial layers (“epilayers”) of silicon-containing materials (e.g., Si, SiGe and Si:C) into the junctions.
Si:C in the source/drain junction regions has been shown to enhance nFET device performance by inducing tensile stress due to its small atomic size compared to Silicon. In order to reduce series resistance, these junctions also need to be heavily n-doped. For example, phosphorus or arsenic can be used for n-doping. If the Si:C is epitaxially grown in the recessed junction areas, both the concentration of substitutional carbon (Csub) as well as substitutional phosphorus (Psub) need to be as high as possible for high tensile stress as well as for low series resistance. However, Csub is not stable under excessive amounts of thermal stress as the Si:C film is grown under metastable conditions. For instance, most of the stress is lost after a 1050° C. thermal spike anneal. The challenge is to retain the tensile stress in the channel after multiple anneals while keeping the series resistance as low as possible.
Current selective epitaxy processes usually require a high reaction temperature, such as about 800° C., 1,000° C. or higher. Such high temperatures are not desirable during a fabrication process due to thermal budget considerations and possible uncontrolled nitridation reactions to the substrate surface. In addition, most of the C atoms incorporated through typical selective Si:C epitaxy processes at the higher process temperatures occupy non-substitutional (i.e. interstitial) sites of the Si lattice. By lowering growth temperature below about 600° C., a higher fraction of substitutional carbon level can be achieved (e.g. nearly 100% at growth temperature of 550° C.), however, the slow growth rate at these lower temperatures is undesirable for device applications, and such selective processing might not be possible at the lower temperatures.
The manufacturing conditions for silicon carbon epitaxy may be different for epitaxy having different dopants and dopant concentrations. The incorporation of high levels of dopants (e.g. greater than 1020 atoms/cm3) into the Si:C epitaxy during deposition is of interest, because the incorporation of high levels of dopants during deposition reduces the need to increase the dopant level using subsequent procedures such as ion implantation. Also, despite the benefits of Csub, the processing involved in incorporating Csub into the source/drain region may pose significant challenges. Thus, the incorporation of high levels of dopants into the Si:C epitaxy, and eliminating carbon completely in favor of a dopant for creating tensile stress may have beneficial effects on the performance of a device while alleviating significant challenges in the epitaxial processing.
Accordingly, improved and novel methods are required for providing tensile stress in the channel and providing low series resistance while depending less on the presence of substitutional carbon.